Memory device

ABSTRACT

A memory device includes a substrate, first, second, and third conductive layers, a stack of fourth conductive layers, a memory pillar, and an insulator. The first, second, and third conductive layer are provided above the substrate. The stack of fourth conductive layers is provided above the third conductive layer. The memory pillar extends in the thickness direction through the stack and the third conductive layer and into the second conductive layer in a first region of the memory device. The insulator extends in a thickness direction through the stack, the third conductive layer, and the second conductive layer in a second region of the memory device. The insulator also extends in a second surface direction of the substrate. A thickness of the third conductive layer in a region through which the insulator extends is greater than a thickness of the third conductive layer in the first region.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority fromJapanese Patent Application No. 2019-0169365, filed on Sep. 18, 2019,the entire contents of which are incorporated herein by reference.

FIELD

Embodiment described herein relates generally to a memory device.

BACKGROUND

A NAND flash memory having a three-dimensional structure is known.

DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a memory device according to an embodiment.

FIG. 2 is an equivalent circuit diagram of a memory cell array of thememory device according to the embodiment.

FIG. 3 is a diagram showing an example of a layout of the memory cellarray of the memory device according to the embodiment.

FIG. 4 is a cross-sectional diagram showing a structure of the memorycell array of the memory device according to the embodiment.

FIG. 5 is a diagram showing an example of a structure of the memory cellof the memory device of the embodiment.

FIG. 6 is a cross-sectional diagram to show a process of a manufacturingmethod of the memory device according to the embodiment.

FIG. 7 is a plan view diagram to show a process of the manufacturingmethod of the memory device according to the embodiment.

FIG. 8 is a cross-sectional diagram to show a process of themanufacturing method of the memory device according to the embodiment.

FIG. 9 is a cross-sectional diagram to show a process of themanufacturing method of the memory device according to the embodiment.

FIG. 10 is a cross-sectional diagram to show a process of themanufacturing method of the memory device according to the embodiment.

FIG. 11 is a plan view diagram to show a process of the manufacturingmethod of the memory device according to the embodiment.

FIG. 12 is a cross-sectional diagram to show a process of themanufacturing method of the memory device of the embodiment.

FIG. 13 is a cross-sectional diagram to show showing a process of themanufacturing method of the memory device according to the embodiment.

FIG. 14 is a cross-sectional diagram to show a process of themanufacturing method of the memory device according to the embodiment.

FIG. 15 is a cross-sectional diagram to show a process of themanufacturing method of the memory device according to the embodiment.

FIG. 16 is a cross-sectional diagram to show a process of themanufacturing method of the memory device according to the embodiment.

FIG. 17 is a cross-sectional diagram to show a process of themanufacturing method of the memory device of the embodiment.

FIG. 18 is a cross-sectional diagram to show a process of themanufacturing method of the memory device according to the embodiment.

FIG. 19 is a cross-sectional diagram to show a process of themanufacturing method of the memory device according to the embodiment.

DETAILED DESCRIPTION

Embodiments provide a memory device with better characteristics.

In general, according to an embodiment, a memory device includes asubstrate, first, second, and third conductive layers, a stack of fourthconductive layers, a memory pillar, and an insulator. The firstconductive layer is provided above the substrate in a thicknessdirection of the substrate. The second conductive layer is directlyprovided on the first conductive layer. The third conductive layer isdirectly provided on the second conductive layer. The stack of fourthconductive layers is provided above the third conductive layer in thethickness direction. The memory pillar extends in the thicknessdirection through the stack of fourth conductive layers and the thirdconductive layer and into the second conductive layer in a first regionof the memory device. The memory pillar includes a semiconductor layerhaving a side surface in contact with the second conductive layer. Aplurality of memory cells is provided at intersections of the memorypillar and the fourth conductive layers, respectively. The insulatorextends in the thickness direction through the stack of fourthconductive layers, the third conductive layer, and the second conductivelayer in a second region of the memory device that is adjacent to thefirst region in a first surface direction of the substrate. Theinsulator also extends in a second surface direction of the substratedifferent from the first surface direction. A thickness of the thirdconductive layer in a region through which the insulator extends isgreater than a thickness of the third conductive layer in the firstregion.

Hereinafter, embodiments will be described with reference to drawings.Each embodiment shows a device and a method for embodying the technicalidea of the present disclosure. The drawings are schematic orconceptual, and the dimensions and ratios of the drawings are notnecessarily the same as the actual ones. The technical idea of thepresent disclosure is not specified by the shape, structure,arrangement, and the like of the components.

[1] Embodiment

A memory device and a manufacturing method thereof according to anembodiment will be described below with reference to FIGS. 1 to 19.

(A) CONFIGURATION EXAMPLE

A configuration example of the memory device according to the presentembodiment will be described with reference to FIGS. 1 to 5.

FIG. 1 is a block diagram showing a configuration example of the memorydevice according to the present embodiment.

As shown in FIG. 1, a memory device 1 of the present embodiment iselectrically coupled to a memory controller 2.

The memory controller 2 sends a command CMD, address information ADD,and various control signals CNT to the memory device 1 of the presentembodiment.

The memory device 1 receives a command CMD, address information ADD, andvarious control signals CNT. Data DAT is transferred between the memorydevice 1 and the memory controller 2. Hereinafter, the data DATtransferred from the memory controller 2 to the memory device 1 during awrite operation is referred to as write data. The write data DAT iswritten in the memory device 1. Data DAT transferred from the memorydevice 1 to the memory controller 2 during a read operation is referredto as read data. Read data DAT is read from the memory device 1.

The memory device 1 of the present embodiment includes, for example, amemory cell array 10, a command register 11, an address register 12, asequencer 13, a driver circuit 14, a row control circuit 15, and a senseamplifier circuit 16.

The memory cell array 10 stores data. A plurality of bit lines and aplurality of word lines are provided in the memory cell array 10. Thememory cell array 10 includes a plurality of blocks BLK0 to BLKn (n isan integer of 1 or more). The block BLK is a set of a plurality ofmemory cells and is used as a data erasing unit, for example. Eachmemory cell is associated with one bit line and one word line. Theconfiguration of the memory cell array 10 will be described below.

The command register 11 stores a command CMD from the memory controller2. The command CMD includes, for example, instructions that cause thesequencer 13 to execute a read operation, a write operation, an erasingoperation, and the like.

The address register 12 stores address information ADD from the memorycontroller 2. The address information ADD includes, for example, a blockaddress, a page address, and a column address. For example, the blockaddress, page address, and column address are used to select a blockBLK, a word line, and a bit line, respectively. In the following, ablock selected based on a block address is referred to as a selectedblock. A word line selected based on a page address is referred to as aselected word line.

The sequencer 13 controls the operation of the entire memory device 1.For example, the sequencer 13 controls the driver circuit 14 based onthe command CMD in the command register 11.

The driver circuit 14 outputs a voltage used in a read operation, awrite operation, an erasing operation, and the like to the memory cellarray 10. Based on the page address in the address register 12, thedriver circuit 14 applies a predetermined voltage to, for example, awiring corresponding to the selected word line.

The row control circuit 15 controls operations related to the rows ofthe memory cell array 10. The row control circuit 15 selects one blockBLK in the memory cell array 10 based on the block address in theaddress register 12. For example, the row control circuit 15 transfersthe voltage applied to the wiring corresponding to the selected wordline to the selected word line in the selected block BLK.

The sense amplifier circuit 16 controls operations related to thecolumns of the memory cell array 10. In a write operation, the senseamplifier circuit 16 applies a voltage to each of the bit lines providedin the memory cell array 10 in accordance with the write data DAT fromthe memory controller 2. In a read operation, the sense amplifiercircuit 16 determines the data stored in the memory cell based on thepotential of the bit line (or the presence or absence of currentgeneration). The sense amplifier circuit 16 transfers data based on thedetermination result to the memory controller 2 as read data DAT.

For example, the memory device 1 is a NAND flash memory.

In this case, communication between the memory device 1 and the memorycontroller 2 is supported by, for example, the NAND interface standard.For example, in the communication between the memory device 1 and thememory controller 2, a command latch enable signal CLE, an address latchenable signal ALE, a write enable signal WEn, a read enable signal REn,a ready busy signal RBn, and an input/output signal IO are used.

The command latch enable signal CLE is a signal indicating that theinput/output signal IO received by the memory device 1 is a command CMD.The address latch enable signal ALE is a signal indicating that thesignal IO received by the memory device 1 is address information ADD.The write enable signal WEn is a signal for instructing the memorydevice 1 to input an input/output signal IO. The read enable signal REnis a signal for instructing the memory device 1 to output aninput/output signal I/O.

The ready/busy signal RBn is a signal for notifying the memorycontroller 2 whether the memory device 1 is in a ready state in which aninstruction from the memory controller 2 is received or is in a busystate in which an instruction is not received. The input/output signalIO is, for example, an 8-bit width signal, and may include a commandCMD, address information ADD, data DAT, and the like.

The memory device 1 and the memory controller 2 may constitute onesemiconductor device (memory system or storage device) by a combinationthereof. Examples of such a semiconductor device include a memory cardsuch as an SD™ card and a solid state drive (SSD).

In the NAND flash memory 1 according to the embodiment, a control unitreferred to as a plane may be formed by a configuration (control unit)including the memory cell array 10, the row control circuit 15, and thesense amplifier circuit 16. FIG. 1 shows an example in which the NANDflash memory 1 has one plane. However, the NAND flash memory 1 mayinclude two or more planes. The configuration of the plane is notlimited to the above configuration, and the plane only needs to includeat least the memory cell array 10.

<Circuit Configuration>

FIG. 2 is an equivalent circuit diagram showing an example of a circuitconfiguration of the memory cell array 10 of the memory device (NANDflash memory) 1 according to the embodiment. In FIG. 2, one block BLK isextracted from the plurality of blocks BLK in the memory cell array 10.

As shown in FIG. 2, the block BLK includes, for example, four stringunits SU0, SU1, SU2, and SU3. Each string unit SU includes a pluralityof memory cell strings (hereinafter, referred to as NAND strings) NS.Each of the plurality of NAND strings NS is associated with acorresponding one of a plurality of bit lines BL0 to BLm (m is aninteger of 1 or more).

The NAND string NS includes a plurality of memory cells MC0 to MC7 andselect transistors ST1 and ST2.

For example, eight memory cells MC are provided in each NAND string NS.The number of memory cells MC in the NAND string NS is not limited toeight.

For example, each select transistor ST1 may include one or moretransistors.

A memory cell (hereinafter, also referred to as a memory celltransistor) MC is a field effect transistor including a charge storagelayer. The memory cell MC can store data of 1 bit or more substantiallyin a nonvolatile manner.

Each of the select transistors ST1 and ST2 is used to select the stringunit SU during various operations.

In each NAND string NS, the memory cells MC0 to MC7 are coupled inseries between the source of the select transistor ST1 and the drain ofthe select transistor ST2. Control gates of the memory cells MC0 to MC7in the same block BLK are commonly coupled to a corresponding one of aplurality of word lines WL0 to WL7.

In each NAND string NS, the drain of the select transistor ST1 iscoupled to the corresponding bit line BL.

One end of the select transistor ST1 is coupled to one end of the memorycells MC0 to MC7 coupled in series, and the other end of the selecttransistor ST1 is coupled to the corresponding bit line BL.

The gate of the select transistor ST1 is coupled to a correspondingselect gate line SGD.

The gate of the select transistor ST1 in the string unit SU0 is coupledto a select gate line SGD0. The gate of the select transistor ST1 in thestring unit SU1 is coupled to a select gate line SGD1. The gate of theselect transistor ST1 in the string unit SU2 is coupled to a select gateline SGD2. The gates of the select transistors ST1 in the string unitSU3 are coupled to a select gate line SGD3, respectively.

The sources of a plurality of select transistors ST2 in the same blockBLK are commonly coupled to a source line SL. The gates of the pluralityof select transistors ST2 in the same block BLK are commonly coupled toa select gate line SGS.

In the circuit configuration of the memory cell array 10 describedabove, the drains of the select transistors ST1 corresponding to thesame column among the plurality of blocks BLK are coupled to the samebit line BL. For example, the source line SL is commonly coupled betweenthe plurality of blocks BLK.

A plurality of memory cells MC coupled to a common word line WL in onestring unit SU are referred to as, for example, a cell unit CU.

For example, when each of the memory cells MC stores 1-bit data, onecell unit CU can store one page data, and when each of the memory cellsMC stores 2-bit data, one cell unit CU can store two page data. “Onepage data” is defined by the total amount of data stored in a cell unitCU composed of memory cells MC storing 1-bit data, for example.

The circuit configuration of the memory cell array 10 of the memorydevice 1 of the embodiment is not limited to the above-describedconfiguration. For example, the number of memory cells MC and selecttransistors ST1 and ST2 in each NAND string NS may be any number. Thenumber of string units SU in each block BLK may be any number.

<Example of Structure>

An example of the structure of the memory device (NAND flash memory)according to the embodiment will be described with reference to FIGS. 3and 5.

As will be described below, in the NAND flash memory 1 of theembodiment, the memory cell array 10 is provided above the surface (XYplane and upper surface) of the semiconductor substrate in a direction(Z direction) perpendicular to the surface of the semiconductorsubstrate. The X and Y directions may be referred to as surfacedirections of the semiconductor substrate, and the Z direction may bereferred to as a thickness direction of the semiconductor substrate.

For example, the NAND flash memory 1 of the present embodiment may havea structure in which a circuit (hereinafter, referred to as CMOS circuitor peripheral circuit) such as the sense amplifier circuit 16 isprovided between the surface of the semiconductor substrate and thememory cell array 10 (below the memory cell array 10 in the Zdirection).

In the drawings referred to below, the X direction corresponds to theextending direction of the word line WL, the Y direction corresponds tothe extending direction of the bit line BL, and the Z directioncorresponds to a direction perpendicular to the upper surface of thesemiconductor substrate 20 on which the semiconductor memory 1 isformed.

In the cross-sectional views referred to below, components such as aninsulating layer (interlayer insulating film), wiring, and contacts areomitted as appropriate for visibility and simplification of thedrawings. In the plan view, hatching is appropriately added forvisibility of the drawing and identification of the components. Thehatching added to the plan view is not necessarily related to thematerial and characteristics of the components to which the hatching isadded.

(Planar Layout of Memory Cell Array)

FIG. 3 illustrates an example of a planar layout of the memory cellarray of the NAND flash memory according to the embodiment. In FIG. 3,one block of the memory cell array is extracted and shown.

As shown in FIG. 3, a plurality of slits SLT are provided in the memorycell array 10. The slit SLT includes a portion extending in the Xdirection. For example, an insulator is provided in the slit SLT.

A slit SHE is provided between two slits SLT arranged in the Ydirection. The slit SHE includes a portion extending in the X direction.For example, an insulator is provided in the slit SHE.

A plurality of memory pillars MP are provided in the memory cell array10. For example, the plurality of memory pillars MP are arranged in thememory cell array 10 in a staggered manner. The memory pillar MP has acolumnar (or elliptical columnar) structure. For example, one memorypillar MP is used for one NAND string NS.

A set of a plurality of memory pillars MP in a region between the slitSLT and the slit SHE corresponds to one string unit SU.

The string unit SU extends along the X direction. The string units SU0to SU3 are arranged in the Y direction.

In one block BLK, one slit SLT is provided between two string units SU1and SU2 between two slits SHE. The two string units SU are providedbetween the two slits SLT in the Y direction. A slit SHE is providedbetween the two string units SU between the two slits SLT.

The plurality of memory pillars MP are arranged in a staggered manner ina region between the slit SLT and the slit SHE. In the following, aregion R1 (the region between the two slits SLT) where the memory pillaris provided is referred to as a cell region R1. A region R2 where theslit SLT (insulator 60) is provided is referred to as a slit region R2.The slit region R2 includes a portion adjacent to the cell region R1 inthe Y direction. A region R3 where the slit SHE is provided is referredto as a dummy region R3. The dummy region R3 may be regarded as a partof the cell region R1.

For example, a hookup region (not shown) is provided in the memory cellarray 10 so as to be adjacent to the cell region in the X direction. Thehookup region is a region where plurality of contact plugs are provided.The contact plugs in the hookup region electrically couple the selectgate lines SGD and SGS coupled to the NAND string NS, the word line WL,the source line SL, and the wiring coupled to the memory cell array 10to the CMOS circuit.

For example, dummy cells may be provided in the memory cell array 10.The dummy cell has substantially the same structure as the memory cell.The dummy cell is formed by using a dummy pillar. The dummy pillar hassubstantially the same structure as the memory pillar MP. The dummy cellis not used for data storage.

(Cross-Sectional Structure of Memory Cell Array)

FIG. 4 illustrates an example of a cross-sectional structure of thememory cell array of the NAND flash memory according to the embodiment.FIG. 4 shows a cross-sectional structure along the Y direction of thememory cell array.

As shown in FIG. 4, conductive layers 21A, 21B, 21C, 22, 23, and 24 arestacked above a semiconductor substrate 20 in the Z direction.

The conductive layer 21A is provided above the semiconductor substrate20 via an insulator (not shown).

The conductive layer 21B is provided on the conductive layer 21A. Forexample, the conductive layer 21B is in direct contact with theconductive layer 21A. For example, the conductive layer 21B includes afirst layer 210 and a second layer 211. The two layers 210 and 211 maybe continuous layers or non-continuous layers (layers having aninterface between the layers 210 and 211).

A conductive layer 21C is provided on the conductive layer 21B. In theslit region R2, the conductive layer 21C faces the side surface (surfaceintersecting the Y direction) of the conductive layer 21B. For example,the conductive layer 21C is in direct contact with the layer 211 of theconductive layer 21B.

The conductive layer 21C has a different dimension (film thickness) inthe Z direction between the cell region R1 and the slit region R2. Theconductive layer 21C has a portion 215 in the cell region R1 and aportion 216 in the slit region R2.

A dimension D2 of the conductive layer 21C (portion 216) in the slitregion R2 in the Z direction is larger than the dimension D1 theconductive layer 21C (portion 215) in the cell region R1 in the Zdirection. The portion having the dimension D2 of the conductive layer21C covers the side surface of the conductive layer 21B.

The conductive layers 21A, 21B, and 21C are electrically coupled to eachother. The conductive layers 21A, 21B, and 21C have, for example, aplate-like structure that spreads along the XY plane.

The conductive layers 21A, 21B, and 21C are used as source lines SL (orsource line contacts).

For example, the conductive layers 21A and 21C are also used as etchingstopper layers in the process of forming the memory cell array 10.

The conductive layers 21A, 21B, and 21C are semiconductor layers. Forexample, the dopant concentration (impurity concentration) of theconductive layer 21A is lower than the dopant concentration of theconductive layer 21B. The impurity concentration of the conductive layer21A may be different from the dopant concentration of the conductivelayer 21C.

The conductive layers 21A and 21C are, for example, non-dopedpolysilicon layers. The conductive layer 21B is, for example, aconductive silicon layer (for example, a polysilicon layer doped withphosphorus). At least one of the materials of the conductive layers 21Aand 21C may be the same as the material (for example, conductivepolysilicon) of the conductive layer 21B.

As described above, below the memory cell array 10 in the Z direction, aCMOS circuit (not shown) such as a row control circuit and a senseamplifier circuit is provided in an insulator (not shown) between theupper surface of the semiconductor substrate 20 and the conductive layer21A.

The conductive layer 22 is provided on the conductive layer 21C via aninsulating layer (not shown). The conductive layer 22 has, for example,a plate-like structure that spreads along the XY plane. The conductivelayer 22 is used as the select gate line SGS. The conductive layer 22is, for example, a metal layer (for example, a tungsten layer or a layercontaining tungsten).

A plurality of conductive layers 23 are provided above the conductivelayer 22. The conductive layers 23 and insulating layers (not shown) arealternately stacked on the conductive layer 22 in the Z direction. Theconductive layer 23 has, for example, a plate-like structure thatspreads along the XY plane. The plurality of stacked conductive layers23 are used as the word lines WL0 to WL7 in order from the semiconductorsubstrate 20 side. The conductive layer 23 is, for example, a metallayer (tungsten layer or a layer containing tungsten).

One or more conductive layers 24 are provided above the uppermostconductive layer 23 (the layer located on the most opposite side withrespect to the semiconductor substrate side). The conductive layers 24and insulating layers (not shown) are alternately stacked on theuppermost conductive layer 23 in the Z direction. The conductive layer24 has, for example, a plate-like structure that spreads along the XYplane. The conductive layer 24 is, for example, a metal layer (tungstenlayer or a layer containing tungsten).

The conductive layers 22, 23, and 24 may be conductive polysiliconlayers, for example.

Hereinafter, the structure including the conductive layers 22, 23 and 24and the insulating layers is referred to as a stacked body 200.

The conductive layer 25 is provided above the conductive layer 24 in theZ direction via an insulating layer (not shown). The conductive layer 25has a linear structure extending along, for example, the Y direction.The conductive layer 25 is used as the bit line BL. The plurality ofconductive layers 25 are arranged in the X direction (the depthdirection or the front direction in the drawing). The conductive layer25 is a metal layer (for example, copper (Cu)).

The memory pillar MP has a columnar structure extending along the Zdirection. The memory pillar MP passes through the stacked body 200 (aplurality of stacked conductive layers 22, 23, and 24).

For example, the upper end of the memory pillar MP in the Z direction isdisposed in a region between the region (height) where the conductivelayer 24 is provided and the region where the conductive layer 25 isprovided in the Z direction.

The lower end of the memory pillar MP in the Z direction is provided inthe source line SL. For example, the lower end of the memory pillar MPis disposed in a region where the conductive layer 21B is provided inthe Z direction. The lower end of the memory pillar MP is in contactwith the conductive layer 21B without penetrating the conductive layer21B. The conductive layer 21B is provided between the lower end of thememory pillar MP and the conductive layer 21A.

The lower end of the memory pillar MP is an end portion on thesemiconductor substrate 20 side in the Z direction of the memory pillar,and the upper end of the memory pillar MP is an end portion facing thelower end of the memory pillar MP in the Z direction.

The side surface of the memory pillar MP (the surface along the Zdirection of the memory pillar MP) faces the conductive layers 22, 23,and 24 (and the insulating layers).

The memory pillar MP includes, for example, a core layer 30, asemiconductor layer (conductive layer) 31, and a memory layer 32.

The core layer 30 has a columnar structure extending along the Zdirection. For example, the upper end of the core layer 30 is disposedin a region between the region where the uppermost conductive layer 24is provided and the region where the conductive layer 25 is provided.For example, the lower end of the core layer 30 is disposed in a regionwhere the conductive layer 21B is provided. The core layer 30 includesan insulator such as silicon dioxide (SiO₂), for example.

The semiconductor layer 31 is provided between the core layer 30 and thememory layer 32. The semiconductor layer 31 has a portion in directcontact with the conductive layer 21B in the region where the conductivelayer 21B is provided. By this portion, the semiconductor layer 31 iselectrically coupled to the conductive layer 21B.

For example, the semiconductor layer 31 covers the core layer 30. Theside surface and the lower surface of the semiconductor layer 31 arecovered with the memory layer 32 except for a portion where thesemiconductor layer 31 is in contact with the conductive layer 21B. Theupper end of the core layer 30 may not be covered with the semiconductorlayer 31.

The semiconductor layer 31 (hereinafter, also referred to as aconductive layer) is, for example, a layer containing silicon (forexample, a polysilicon layer or an amorphous silicon layer).

The memory layer 32 is provided between the stacked body 200 and thesemiconductor layer 31. A side surface (surface along the Z direction)of the memory layer 32 faces the conductive layers 22, 23, and 24. Anopening is provided in the memory layer 32 in a region where thesemiconductor layer 31 is in contact with the conductive layer 21B. Thesemiconductor layer 31 is provided between the lower end (bottomportion) of the core layer 30 and the memory layer 32.

The memory layer 32 is a stacked film including a plurality of layers.The structure of the memory layer 32 will be described with reference toFIG. 5.

FIG. 5 shows an example of a cross-sectional structure of the memorypillar in a cross section parallel to the upper surface of thesemiconductor substrate 20.

As shown in FIG. 5, the memory pillar MP has a circular (or elliptical)planar shape.

In the region including the conductive layer (word line) 23, the corelayer 30 is provided at the center of the memory pillar MP. Thesemiconductor layer 31 is provided between the side surface of the corelayer 30 and the memory layer 32. The memory layer 32 is providedbetween the side surface of the semiconductor layer 31 and theconductive layer 23. The memory layer 32 includes, for example, aninsulating layer 321, a charge storage layer 322, and an insulatinglayer 323.

The charge storage layer 322 is provided between the two insulatinglayers 321 and 323. The charge storage layer 322 covers the sidesurfaces of the insulating layers 321 and 323.

An amount of charges corresponding to data to be stored is stored in thecharge storage layer 322. For example, as the charge storage layer 322,a charge trap film (for example, a silicon nitride film) including traplevels is used. With respect to the charge storage layer 322 using thecharge trap film, charges are trapped in trap levels in the chargestorage layer 322. The threshold voltage of the memory cell MC changesdepending on the amount of charges in the charge storage layer 322.

An insulating layer 321 (hereinafter, also referred to as a blockinsulating layer) is provided between the charge storage layer 322 andthe conductive layer 23. The block insulating layer 321 is providedbetween the charge storage layer 322 and the conductive layer 23. Theblock insulating layer 321 covers the side surface of the charge storagelayer 322. The block insulating layer 323 is in contact with theconductive layer 23.

The block insulating layer 321 prevents electrons from moving betweenthe charge storage layer 322 and the conductive layer 23 as a potentialbarrier. For example, the block insulating layer 321 is an insulatingoxide film (for example, an aluminum oxide film).

The insulating layer 323 (hereinafter, also referred to as a gateinsulating layer or a tunnel insulating layer) is provided between thesemiconductor layer 31 and the charge storage layer 322. The gateinsulating layer 323 covers the side surface of the semiconductor layer31. The gate insulating layer 323 is in contact with the semiconductorlayer 31.

The gate insulating layer 323 functions as a gate insulating layer ofthe memory cell MC. The gate insulating layer 323 functions as a tunnelbarrier between the charge storage layer 322 and the semiconductor layer31. For example, the gate insulating layer 323 is formed by using aninsulating oxide layer (for example, a silicon oxide film).

Each of the layers 321, 322, and 323 is continuous from the top to thebottom of the stacked body 200 in the Z direction. Each of the layers321, 322, and 323 is provided between the stacked body 200 and thesemiconductor layer 31 in the memory hole.

Returning to FIG. 4, regarding the relationship between the memorypillar MP and the NAND string NS, for example, a select transistor ST2is provided in a portion where the memory pillar MP faces the conductivelayer 22. A memory cell MC is provided in a portion where the memorypillar MP faces the conductive layer 23. The select transistor ST1 isprovided in a portion where the memory pillar MP faces the conductivelayer 24. The conductive layer (semiconductor layer) 31 in the memorypillar MP functions as a channel region of each of the memory cell MCand the select transistors ST1 and ST2.

A contact plug CH is provided between the memory pillar MP and theconductive layer 25. The contact plug CH is, for example, a metal layer.The upper end of the contact plug CH is in contact with one conductivelayer 25 (bit line BL). The lower end of the contact plug CH is incontact with the upper end of the semiconductor layer 31. As a result,the bit line BL is electrically coupled to the NAND string NS (memorypillar MP).

In the region R3, an insulator 61 is provided in the slit SHE. Theinsulator 61 in the slit SHE includes, for example, silicon oxide.

The insulator 61 has a plate-like structure extending along the XZplane. The conductive layer 24 is divided in the Y direction by theinsulator 61 (and the slit SHE). The insulator 61 covers the upper endof the semiconductor layer 31.

For example, the upper end of the insulator 61 is disposed in a regionbetween the region where the upper end of the memory pillar MP isprovided and the region where the conductive layer 25 is provided. Forexample, the lower end of the insulator 61 is disposed between a regionwhere the uppermost conductive layer 23 is provided and a region wherethe conductive layer 24 is provided. For example, a portion where thememory pillar DMP below the insulator 61 faces the conductive layer 23is a dummy cell.

The region R2 where the slit SLT is provided is provided in the blockBLK at a certain cycle, for example. A plurality of slit regions R2 arearranged in the Y direction. The slit region R2 may have a portionextending in the Y direction so as to couple a plurality of portionsextending in the X direction of the slit region R2.

The insulator 60 is provided in the slit SLT. The insulator 60 in theslit SLT includes, for example, silicon oxide (for example, SiO₂).

The insulator 60 has a plate-like structure extending along the XZplane. The insulator 60 extends in the Z direction between the stackedbody 200 and the source line SL.

The side surface of the insulator 60 faces the conductive layers 22, 23,and 24 (stacked body 200). For example, the conductive layers 22, 23,and 24 are divided in the Y direction by the insulator 60.

For example, the upper end of the insulator 60 is disposed in a regionbetween the region including the upper end of the memory pillar MP andthe region where the conductive layer 25 is provided. The lower end ofthe insulator 60 is disposed, for example, in a region where theconductive layer 21A is provided.

The lower end of the insulator 60 is provided in the source line SL. Thelower end of the insulator 60 (and the slit SLT) is disposed, forexample, in a region (height) where the conductive layer 21A is providedwithout penetrating the conductive layer 21A.

For example, a portion of the insulator 60 (a portion of the insulator60 in the source line SL) in a region (height) below the lower end ofthe stacked body 200 is covered with an insulating layer 29. Theconductive layers 21A, 21B, and 21C face the side surface of theinsulator 60 with the insulating layer 29 interposed therebetween. Theinsulating layer 29 is provided between the conductive layers 21A, 21B,21C and the insulator 60. The insulating layer 29 is provided betweenthe lower end (bottom portion) of the insulator 60 and the upper surfaceof the conductive layer 21A.

For example, the position of the lower end of the insulator 60 (thelower end of the slit SLT) in the Z direction is provided closer to thesemiconductor substrate 20 than the position of the lower end of thememory pillar MP in the Z direction.

The dimensions (length and height) of the insulator 60 in the Zdirection are larger than the dimensions of the memory pillar MP in theZ direction.

The insulating layer 29 includes a first portion 290 and a secondportion 291. The insulating layer 29 is a layer containing, for example,silicon oxide.

The first portion 290 covers the side surface and the bottom surface ofthe insulator 60 in the region where the conductive layers 21A, 21B, and21C are provided.

The second portion 291 (hereinafter, also referred to as a protrudingportion) is provided, for example, in a region where the conductivelayer 21B is provided (region in the vicinity of the boundary betweenthe conductive layer 21B and the conductive layer 21A). The secondportion 291 protrudes from the first portion 290 in the Y direction. Forexample, the second portion 291 is provided between the conductive layer21A and the conductive layer 21C in the Z direction. Regarding theposition (height) in the Z direction, the second portion 291 is locatedcloser to the semiconductor substrate than the lower end of the memorypillar MP. Regarding the position in the Z direction, the second portion291 is located on the bit line side (opposite to the semiconductorsubstrate side) from the lower end of the insulator 60. For example, thesecond portion 291 separates the conductive layer 21C from theconductive layer 21A.

For example, the conductive layer 24 is separated into four portions bythe slits SLT and SHE. The four separated portions in the conductivelayer 24 correspond to the string units SU0 to SU3 as the select gatelines SGD, respectively.

(b) MANUFACTURING METHOD

A manufacturing method of the memory device (for example, NAND flashmemory) of the present embodiment will be described with reference toFIGS. 6 to 19.

FIG. 6 is a cross-sectional diagram to illustrate a process in themanufacturing method of the flash memory according to the presentembodiment. In FIG. 6, a cross section (ZY plane) along the Y directionis shown.

As shown in FIG. 6, the conductive layer 21A is formed on an insulator(not shown) that covers the upper surface of the semiconductor substrate20 by, for example, chemical vapor deposition (CVD). The conductivelayer 21A is, for example, a non-doped polysilicon layer.

A conductive layer 210X is formed on the conductive layer 21A by, forexample, CVD. The conductive layer 210X is, for example, a conductivepolysilicon layer (for example, a polysilicon layer doped withphosphorus).

A CMOS circuit (peripheral circuit) may be formed on the semiconductorsubstrate 20 before the formation of the conductive layers 21A and 210X.An insulator (not shown) is formed on the semiconductor substrate 20 soas to cover the formed CMOS circuit. The conductive layers 21A and 210Xare formed above the semiconductor substrate 20 in the Z direction viathe insulator.

FIG. 7 is a top view diagram to illustrate a step in the method ofmanufacturing the flash memory according to the present embodiment. FIG.8 is a cross-sectional diagram taken along the line Q1-Q1 in FIG. 7.

As shown in FIGS. 7 and 8, in the slit region R2, an opening 90 (groove)is formed in the conductive layer 210X by well-known photolithographyand etching (for example, reactive etching). For example, the opening 90has a linear shape extending in the X direction. When the opening 90 isformed, the upper surface of the conductive layer 210X in the cellregion R1 is covered with a mask layer (not shown). In the presentembodiment, the upper surface of various layers such as the conductivelayer 210X is a surface facing the surface of the layer on thesemiconductor substrate side in the Z direction. The lower surface(bottom surface) of the layer is the surface of the layer on thesemiconductor substrate side in the Z direction.

For example, the dimension of the opening 90 in the Y direction is setto “DA”. The dimension DA is the dimension of the largest dimension (forexample, the upper portion of the opening 90) in the Y direction of theopening 90 when the opening 90 has a tapered cross-sectional shape. Inthe tapered opening 90, a dimension DX of the bottom portion of theopening 90 in the Y direction is smaller than the dimension DA.

The upper surface of the conductive layer 21A is exposed through theopening 90.

As indicated by a broken line 99 in FIG. 8, the upper surface (exposedsurface) of the conductive layer 21A in the opening 90 may recede towardthe semiconductor substrate from the boundary (interface) between theconductive layer 21A and the conductive layer 210X. In this case, withrespect to the position from the upper surface of the semiconductorsubstrate 20 in the Z direction, the position of the upper surface(exposed surface) of the conductive layer 21A in the slit region R2 islower than the position of the upper surface of the conductive layer 21Ain the cell region R1 (position of the boundary between the conductivelayer 21A and the conductive layer 210X).

FIG. 9 is a cross-sectional diagram to illustrate a process in themanufacturing method of the flash memory according to the presentembodiment. In FIG. 9, a cross section along the Y direction (crosssection of the ZY plane) is shown.

As shown in FIG. 9, an insulating layer 218 (hereinafter, referred to asa sacrifice layer or a spacer layer) is formed on the conductive layers21A and 210X by, for example, CVD. Thereby, the sacrifice layer 218covers the upper surface of the conductive layer 21A exposed through theopening 90 and the side surface (side wall) of the conductive layer210X. The side surface of the conductive layer 210X is a surface thatintersects the Y direction (the direction parallel to the upper surfaceof the substrate 20).

An insulating layer 219 (hereinafter, referred to as a sacrifice layeror a spacer layer) is formed on the sacrifice layer 218 by, for example,CVD.

The sacrifice layer 218 is, for example, a silicon oxide layer. Thesacrifice layer 219 is, for example, a silicon nitride layer. Thematerial of the two sacrifice layers 218 and 219 is not limited tosilicon nitride and silicon oxide as long as a desired etchingselectivity is achieved between the two sacrifice layers 218 and 219.

Here, a film thickness t1 of the sacrifice layer 218 and a filmthickness t2 of the sacrifice layer 219 are controlled so that theopening 90 is not blocked by the sacrifice layers 218 and 219. The filmthicknesses t1 and t2 of the sacrifice layers 218 and 219 are set todimensions (here, dimensions in the Y direction) in the directionparallel to the upper surface (front surface) of the semiconductorsubstrate 20. In this case, it is preferable that the sacrifice layers218 and 219 are formed, respectively by controlling the film thicknessest1 and t2 of the sacrifice layers 218 and 219 so that the dimension“2×(t1+t2)” obtained by doubling the sum of the film thickness t1 andthe film thickness t2 is smaller than the dimension DA (maximumdimension in the Y direction) of the opening 90 in the Y direction.

After the formation of the sacrifice layer 219, the conductive layer 21Cis formed on the sacrifice layer 219 by, for example, CVD. Theconductive layer 21C is embedded in the opening 90. The opening 90 isfilled with the conductive layer 21C. The conductive layer 21C coversthe upper surface of the conductive layer 21A, the upper surface of theconductive layer 21C, and the side surface of the conductive layer 210Xvia the sacrifice layers 218 and 219.

For example, the conductive layer 21C is a non-doped polysilicon layer.

The conductive layer 21C has different dimensions in the Z directionbetween the cell region R1 and the slit region R2. The conductive layer21C includes the portion 215 in the cell region R1 and the portion 216in the slit region R2.

The dimension D2 of the portion 216 in the slit region R2 in the Zdirection is larger than the dimension D1 of the portion 215 in the cellregion R1 in the Z direction.

FIG. 10 is a cross-sectional diagram to illustrate a process in themanufacturing method of the flash memory according to the presentembodiment. In FIG. 10, a cross section along the Y direction (crosssection of the ZY plane) is shown.

As shown in FIG. 10, the insulating layer 29 is formed on the conductivelayer 21C by, for example, CVD. An insulating layer 28 is formed on theinsulating layer 29 by, for example, the CVD method. Thereafter, theinsulating layers 29 and the insulating layers 28 are alternately formedin the Z direction.

Thereby, the stacked body 200 including a plurality of insulating layers28 and 29 is formed above the semiconductor substrate 20 in the Zdirection.

For example, the insulating layer 29 is a silicon oxide layer. Theinsulating layer 28 is, for example, a silicon nitride layer. Thematerial of the layers 28 and 29 is not limited as long as a desiredetching selectivity is achieved between the two layers 28 and 29. Forexample, silicon oxide may be used for the material of the layer 29, anda semiconductor (for example, silicon) may be used for the material ofthe layer 28.

In the cell region R1, a plurality of holes MH (hereinafter, referred toas memory holes) are formed in the stacked body 200 by photolithographyand etching (for example, anisotropic etching). A memory hole MH extendsin the Z direction through the stacked body 200. The bottom portion ofthe memory hole MH reaches the conductive layer 210X. For example, atthe position where the hole MH is formed, the upper surface of theconductive layer 210X recedes to the semiconductor substrate 20 side.

The memory layer 32 is formed on the stacked body 200, the sacrificelayers 218 and 219, and the conductive layers 210X and 211X by, forexample, CVD. As described above (for example, FIG. 5), the memory layer32 is a stacked film including three layers. In this case, the chargestorage layer 322 is formed on the block insulating layer 321 after theblock insulating layer 321 is formed. After the formation of the chargestorage layer 322, the gate insulating layer 323 is formed on the chargestorage layer 322.

In the hole MH, the memory layer 32 is formed on the side surfaces ofthe insulating layers 28, 29, 218, and 219, on the side surface of theconductive layer 211X, and on the upper surface of the conductive layer210X. Thus, the exposed portions of the members 28, 29, 210X, 211X, 218,and 219 corresponding to the shape of the hole MH are covered with thememory layer 32 in the hole MH.

The film thickness of the memory layer 32 is controlled to be formed sothat the memory layer 32 does not block the memory hole MH.

The semiconductor layer 31 is formed on the memory layer 32 by, forexample, CVD. The semiconductor layer 31 is a silicon layer. The filmthickness of the semiconductor layer 31 is controlled to be formed sothat the semiconductor layer 31 does not close the hole MH.

The core layer (insulating layer) 30 is formed on the semiconductorlayer 31 by, for example, CVD. The formation of the core layer 30 closesthe memory hole MH.

For example, chemical mechanical polishing (CMP) or etching back isperformed on the core layer 30, the semiconductor layer 31, and thememory layer 32 by using the upper surface of the stacked body 200 as astopper. The core layer 30, the semiconductor layer 31, and the memorylayer 32 are removed from the upper surface of the stacked body 200. Forexample, the upper end of the core layer 30 is covered with asemiconductor layer continuous with the semiconductor layer 31 byre-forming the conductive layer and heating treatment.

As a result, the memory pillar MP is formed in the memory hole MH. Forexample, the position of the upper end of the memory pillar MP in the Zdirection substantially matches the position of the upper surface of thestacked body 200.

On the lower end side of the memory pillar MP, the side surface of thememory pillar MP (the surface intersecting the X direction or Ydirection of the memory pillar MP) is in contact with the sacrificelayers 218 and 219 and the conductive layer 21C. For example, the memorylayer 32 on the bottom side of the memory pillar MP is in direct contactwith the sacrifice layers 218 and 219 and the conductive layer 21C.

The lower end (bottom portion) of the memory pillar MP is in contactwith the conductive layer 210X. For example, the memory layer 32 at thelower end of the memory pillar MP is in direct contact with theconductive layer 210X.

FIG. 11 is a top view diagram to illustrate a step in the method ofmanufacturing the flash memory according to the present embodiment. FIG.12 is a cross-sectional view taken along the line Q2-Q2 of FIG. 11.

As shown in FIGS. 11 and 12, the slit SLT is formed in the slit regionR2 by photolithography and etching. In the present embodiment, etchingfor forming the slit SLT is performed so that the conductive layer 21Cremains at the bottom portion of the slit SLT. For example, theconductive layer 21C is used as an etching stopper layer.

The planar shape of the slit SLT viewed from the Z direction is aquadrangular shape (linear shape) extending in the X direction. Thecross-sectional shape of the slit SLT viewed from the X direction is aquadrangular shape extending in the Z direction.

The slit SLT extends from the upper surface of the stacked body 200 tothe conductive layer 21C in the Z direction. The lower end of the slitSLT in the Z direction is disposed in the conductive layer 21C.

For example, the dimension DB of the slit SLT in the Y direction isequal to or smaller than the dimension DA of the opening 90 of theconductive layer 21A.

The conductive layer 21C is exposed through the slit SLT.

At the position where the slit SLT is formed, the upper surface of theconductive layer 21C recedes to the semiconductor substrate 20 side. Inthe slit region R2, the groove (concave portion) 99 is formed in theconductive layer 21C.

The upper surfaces of the sacrifice layers 218 and 219 are covered withthe conductive layer 21C.

FIG. 13 is a cross-sectional diagram to illustrate a process in themanufacturing method of the flash memory according to the presentembodiment. In FIG. 13, a cross section along the Y direction (crosssection of the ZY plane) is shown.

As shown in FIG. 13, the layer 50 (hereinafter, also referred to as aprotective layer or a spacer layer) is formed on the stacked body 200and in the slit SLT, for example, by CVD. The layer 50 is etched back.The layer 50 is removed from the upper surface of the stacked body 200and the bottom portion (the upper surface of the conductive layer 21C inthe slit SLT) of the slit SLT.

As a result, the protective layer 50 remains in a self-aligned manner onthe side surfaces of the stacked body 200 (side surfaces of theinsulating layers 28 and 29) in the slit SLT and the side surface of theconductive layer 21C. The protective layer 50 extends in the X directionalong the side surface of the stacked body 200.

In the slit SLT, the side surfaces of the insulating layers 28 and 29and the side surface of the conductive layer 21C are covered with theprotective layer 50.

The protective layer 50 is a semiconductor layer, for example. As a morespecific example, the protective layer 50 is a non-doped polysiliconlayer. The material of the protective layer 50 is not limited to siliconas long as the material provides an etching selectivity with respect toother members (for example, the insulating layers 28 and 29 and theconductive layer 211X).

FIGS. 14 and 15 are cross-sectional process views showing a process inthe manufacturing method of the flash memory according to the presentembodiment. In FIGS. 14 and 15, a cross section along the Y direction(cross section of the ZY plane) is shown.

As shown in FIG. 14, the etching on the conductive layer 211X isperformed in a state where the protective layer 50 covers the sidesurfaces of the stacked body 200 and the conductive layer 211X.

As a result, the conductive layer 211X is removed at the positioncorresponding to the slit SLT in the slit region R2. For example, at theposition corresponding to the slit SLT, the upper surface of theconductive layer 21A recedes to the semiconductor substrate 20 side. Asa result, a groove 98 is formed in the upper surface (upper portion) ofthe conductive layer 21A.

By removing the conductive layer 211X, the sacrifice layers 218 and 219are exposed through the slit SLT.

The sacrifice layer (silicon oxide layer) 218 is removed by wet etching.Thereafter, the sacrifice layer (silicon nitride layer) 219 is removedby wet etching.

As shown in FIG. 15, by removing the two sacrifice layers 218 and 219,an air gap (space) AG is formed between the conductive layer 210X andthe conductive layer 21C.

When etching the sacrifice layers 218 and 219, the side surfaces of thestacked body 200 in the slit SLT are covered with the protective layer50.

Therefore, when the sacrifice layers 218 and 219 are etched, the layers28 and 29 in the stacked body 200 are not etched.

FIG. 16 shows the state of etching of the sacrifice layers 218 and 219.

For example, when the slit SLT reaches the conductive layer 21A duringformation of the slit SLT (see FIGS. 11 and 12), the protective layer 50covers the side surfaces of the sacrifice layers 218 and 219. In thiscase, at the time of removing the sacrifice layers 218 and 219, theetching solution is less likely to flow from the Y direction into thesacrifice layers 218 and 219 whose side surfaces in the Y direction arecovered in the protective layer 50 by the protective layer 50. Inaddition, in a certain portion in the memory cell array 10, the inflowof the etching solution from the Y direction to the sacrifice layers 218and 219 may be hindered due to the narrow interval between theconductive layer 210X and the conductive layer 21C.

In the present embodiment, the slit SLT extends in the Y direction, andthe sacrifice layers 218 and 219 are continuous in the Y direction.

Therefore, as shown in FIG. 15, in the region where the etching solutionis not supplied from the X direction, remaining sacrifice layers 218 zand 219 z can be etched by a supply ESy of the etching solution from theY direction.

Thus, in the present embodiment, the sacrifice layers 218 and 219 areremoved relatively cleanly from the region between the conductive layer210X and the conductive layer 21C.

The sacrifice layers 219 and 218 may be removed by the same etchingsolution.

In the present embodiment, the side surface on the lower end side of thememory pillar MP is exposed to the etching solution through the spacegenerated by the removal of the sacrifice layers 218 and 219. The memorylayer 32 at the bottom portion of the memory pillar MP is removed by,for example, wet etching for removing the sacrifice layer 219. As aresult, an opening 95 is formed on the side surface of the memory pillarMP. An etching solution for removing the memory layer may be suppliedafter removing the sacrifice layer 218 separately from the etchingsolution for removing the sacrifice layer 219.

As a result, the conductive layer (semiconductor layer) 31 is exposed tothe space between the two conductive layers 210X and 21C through theopening 95 on the side surface of the memory pillar MP.

FIG. 17 is a cross-sectional diagram to illustrate a process in themanufacturing method of the flash memory according to the presentembodiment. In FIG. 16, a cross section along the Y direction (crosssection of the ZY plane) is shown.

The conductive layer 210 is selectively formed in the space AG betweenthe conductive layer 21C and the conductive layer 210. The supply pathof the formation of the conductive layer 210 in the space AG is a pathfrom the upper side of the conductive layer 21A (the bottom portion ofthe conductive layer 210) to the upper side of the conductive layer 21.For example, selective CVD (supply of the formation of the layer 21) andetching of residual in the space AG are repeatedly performed.

As a result, the conductive layer 211 is embedded between the conductivelayer 21C and the conductive layer 210. The conductive layers 21A, 210,211, and 21C are electrically coupled to each other.

When the conductive layer 211 is a silicon layer, the conductive layer210 is, for example, a silicon layer. When the conductive layer 210 isformed by selective growth of silicon, the conductive layer 210 and theconductive layer 211 become one continuous layer 21B.

The material of the conductive layer 210 may be different from thematerial of the conductive layer 211. In this case, a boundary(interface) is formed between the two non-continuous layers 210 and 211.

The conductive layer 211 is formed on the side surface of thesemiconductor layer 31 of the memory pillar MP through the opening 95 onthe bottom side of the memory pillar MP. The conductive layer 211 is indirect contact with the semiconductor layer 31.

As a result, the conductive layers 21A, 21B, and 21C serving as sourcelines are electrically coupled to the semiconductor layer 31 of thememory pillar MP.

FIG. 18 is a cross-sectional diagram to illustrate a process in themanufacturing method of the flash memory according to the presentembodiment. In FIG. 18, a cross section along the Y direction (crosssection of the ZY plane) is shown.

As shown in FIG. 18, the protective layer covering the side surface ofthe stacked body 200 is removed from the slit SLT. Thus, the insulatinglayers 28 and 29 are exposed through the slits on the side surface ofthe stacked body 200.

For example, when the material of the conductive layers 21A and 21B isthe same as the material of the protective layer, the conductive layer21B is also etched by the same amount as the film thickness of theprotective layer.

FIG. 19 is a cross-sectional diagram to illustrate a process in themanufacturing method of the flash memory according to the presentembodiment. In FIG. 19, a cross section along the Y direction (crosssection of the ZY plane) is shown.

As shown in FIG. 19, oxidation processing is performed on the conductivelayers 21A, 21B, and 21C.

The exposed surfaces of the semiconductor layers (polysilicon layers) ofthe conductive layers 21A, 21B, and 21C are selectively oxidized.Thereby, the insulating layer is formed along the shape of the groove 99of the conductive layers 21A, 21B, and 21C. For example, the portion 290is formed on the upper surface and side surfaces of the conductive layer21A and on the side surfaces of the conductive layers 21B and 21C.

When non-doped polysilicon is used for the conductive layer 21B andphosphorus-doped polysilicon is used for the conductive layer 21B, theoxidizing agent for the oxidation processing is more easily diffusedinto the silicon layer 21B containing phosphorus as compared with thenon-doped silicon layer 21A.

Therefore, the portion 291 protruding in the Y direction is formed inthe conductive layer 21B in the vicinity of the boundary between theconductive layer 21A and the conductive layer 21B.

Oxidation by the oxidation processing hardly occurs in the insulatinglayers 28 and 29 of the stacked body 200 exposed through the slit SLT.

Thereafter, replacement processing for the insulating layer 28 in thestacked body 200 is performed through the slit.

In the replacement processing, after the insulating layer 28 is removedfrom the stacked body 200, a conductive layer is formed in the spacefrom which the insulating layer is removed (the space between theinsulating layers 28 adjacent in the Z direction).

As a result, the conductive layer (word line) 23 is formed in thestacked body 200 as shown in FIG. 4.

After the formation of the conductive layer 23, the insulator 60 isembedded in the slit SLT. Further, after the formation of the slit SHE,the insulator 61 is formed in the slit SHE.

Thereafter, contact plugs and bit lines BL are subsequently formed by aknown technique. In the hook-up region, contact plugs and wiring areformed.

The NAND flash memory of the present embodiment is completed through theabove processes.

(C) SUMMARY

The NAND flash memory of the present embodiment has a structure in whichthe source line is electrically coupled to the semiconductor layer(conductive layer) in the memory pillar through the opening on the sidesurface of the memory pillar.

In the present embodiment, the source line (or source line contact)includes the three layers 21A, 21B, and 21C. The conductive layer 21B isprovided between the two conductive layers 21A and 21B in the Zdirection. The conductive layer 21C functions as a stopper layer whenforming the slit. The dimension of the conductive layer 21C (portion216) in the slit region in the Z direction is larger than the dimensionof the conductive layer 21C (portion 215) in the cell region in the Zdirection.

In a flash memory having a certain structure, the dimension of thestopper layer in the Z direction for forming the slit is constantbetween the cell region and the slit region. When the dimension of thestopper layer in the Z direction is thin, an unintended layer may beexposed to the slit due to variations of etching in the Z direction inthe slit forming process. In the process of removing a layer through theslit, an unintentionally exposed layer may be exposed to the etchingconditions of the layer and removed. As a result, defects can occur inthe flash memory.

In the present embodiment, the relatively thick stopper layer can reduceprocessing defects due to variations in the etching depth direction inthe slit formation region.

As described above, the flash memory according to the present embodimentcan improve the process robustness against the variations in the etchingdepth direction when a slit is formed. Accordingly, the flash memoryaccording to the present embodiment can improve the manufacturing yieldof the flash memory.

In the present embodiment, the distance between the conductive layer 21Band the conductive layer 22 can be reduced in the cell region whileproviding a thick stopper layer in the slit region. For example, aconductive layer (for example, an impurity semiconductor layer) used forthe source line is used as a dopant diffusion source to thesemiconductor layer of the memory pillar.

In the present embodiment, since the dimension of the stopper layer 21Cin the cell region in the Z direction is small, the distance between theconductive layer 22 serving as the select gate line on the source sideand the conductive layer 21B serving as the dopant diffusion source isreduced. Therefore, the dopant (for example, phosphorus) in theconductive layer 21B easily reaches the portion of the memory pillarfacing the conductive layer 22 by the diffusion of the dopant. As aresult, the flash memory of the present embodiment can improve thecharacteristics of the select transistor on the source side.

In a flash memory having a certain structure, any of a plurality oflayers constituting a select gate line on the source side of a cellstring may be used as a stopper layer at the time of forming a slit. Inthis case, depending on the material of the stopper layer, theresistance value of the select gate line on the source side may be high.

In the flash memory of the present embodiment, the select gate line onthe source side of the NAND string may be configured without using astopper layer for forming a slit.

As a result, the flash memory of the present embodiment can reduce theresistance value of the select gate line on the source side of the cellstring.

As a result, the flash memory of the present embodiment can reduce thewiring delay (for example, RC delay) of the select gate line on thesource side of the NAND string.

As described above, the memory device of the present embodiment canimprove the characteristics.

(D) OTHERS

In this specification, “coupled” does not exclude a case where anothercomponent is interposed between two coupled components. In thisspecification, the term “contact” does not exclude the presence of othercomponents between two components in contact.

While certain embodiments have been described, these embodiments havebeen presented by way of example only, and are not intended to limit thescope of the inventions. These novel embodiments can be implemented invarious other forms, and various omissions, replacements, and changescan be made without departing from the spirit of the invention. Theseembodiments and modification examples thereof are included in the scopeand gist of the invention and are included in the invention described inthe claims and the equivalent scope thereof.

What is claimed is:
 1. A memory device comprising: a substrate; a firstconductive layer provided above the substrate in a thickness directionof the substrate; a second conductive layer directly provided on thefirst conductive layer; a third conductive layer directly provided onthe second conductive layer; a stack of fourth conductive layers that isprovided above the third conductive layer in the thickness direction; amemory pillar extending in the thickness direction through the stack offourth conductive layers and the third conductive layer and into thesecond conductive layer in a first region of the memory device, thememory pillar including a semiconductor layer having a side surface incontact with the second conductive layer, and a plurality of memorycells being provided at intersections of the memory pillar and thefourth conductive layers, respectively; and an insulator extending inthe thickness direction through the stack of fourth conductive layers,the third conductive layer, and the second conductive layer in a secondregion of the memory device that is adjacent to the first region in afirst surface direction of the substrate, the insulator also extendingin a second surface direction of the substrate different from the firstsurface direction, wherein a thickness of the third conductive layer ina region through which the insulator extends is greater than a thicknessof the third conductive layer in the first region.
 2. The memory deviceaccording to claim 1, wherein the first, second, and third conductivelayers collectively serve as a source line of the plurality of memorycells.
 3. The memory device according to claim 1, wherein each of thefourth conductive layers serves as a word line of one of the pluralityof memory cells.
 4. The memory device according to claim 1, wherein animpurity concentration of the second conductive layer is higher than animpurity concentration of the first conductive layer and higher than animpurity concentration of the third conductive layer.
 5. The memorydevice according to claim 1, wherein each of the first, second, andthird conductive layer is a polysilicon layer.
 6. The memory deviceaccording to claim 1, wherein the insulator is formed of silicon oxide.7. The memory device according to claim 1, wherein a distance from thesubstrate to the memory pillar is longer than a distance from thesubstrate to the insulator.
 8. The memory device according to claim 1,wherein the memory pillar does not extend into the first conductivelayer, and the insulator extends into the first conductive layer.
 9. Thememory device according to claim 1, further comprising: a firstinsulating layer provided between a side surface of the insulator andthe first, second and third conductive layers, wherein the firstinsulating layer includes a portion protruding into the secondconductive layer in a surface direction of the substrate.
 10. The memorydevice according to claim 9, wherein the first insulating layer is indirect contact with the side surface of the insulator.
 11. The memorydevice according to claim 9, wherein the first insulating layer is alsoprovided between a bottom surface of the insulator and the firstconductive layer.
 12. The memory device according to claim 11, whereinthe first insulating layer is in direct contact with the bottom surfaceof the insulator.
 13. The memory device according to claim 9, whereinthe first insulating layer is formed of silicon oxide.
 14. The memorydevice according to claim 9, wherein the portion of the first insulatinglayer is in direct contact with the second conductive layer.
 15. Thememory device according to claim 9, wherein the portion of the firstinsulating layer is in direct contact with the first conductive layer.16. The memory device according to claim 1, wherein the secondconductive layer includes a first layer directly provided on the firstconductive layer and a second layer directly provided on an uppersurface and a side surface of the first layer, and the second layer isin contact with the side surface of the semiconductor layer.
 17. Thememory device according to claim 16, wherein the first layer is also incontact with the side surface of the semiconductor layer.
 18. The memorydevice according to claim 1, wherein the first conductive layer is indirect contact with the substrate.